Single Diffused Device Fabrication
Introduction
In order that you may understand the flexibility which planar technology
affords the circuit designer, we have designed a set of test masks (the
Holberg Masks, see pp. 38-47) for use in this lab. This mask set contains
device test structures, resolution bars, and alignment verniers. The devices
fabricated include several MOS transistors, as well as diodes and MOS capacitors.
We will also check diffused resistors, metal step coverage, and metal and
contact resistance. In addition to the device chips, we will process, in
parallel, unpatterned test chips. These samples will allow us to make several
measurements we could not make on our device arrays. You will start with
four chips, two identical n-type samples and two identical p-type samples.
You will pattern one each of the n-type and p-type chips, as described below,
to make your device arrays. The remaining two chips will serve as materials
properties test (MPT) samples allowing you to determine such properties
as oxide thickness, doping concentration, sheet resistance, and junction
depth. Several of these measurements would be destructive or not possible
on the patterned device array chips. This is why we process the MPT samples
in parallel with the device samples.
Processing Description: Device Array Chips
Starting with an oxidized wafer, a pattern will be etched through the oxide
using Mask Level 1 (p. 39) and the Photo-Resist (PR) process outline in
OP-L for use with the Positive Resist. The wafer will then be subjected
to a boron or phosphorus ambient at high temperature so that the dopant
will diffuse into the silicon through the holes in the oxide, forming doped
regions on the wafer in those areas delineated by Mask 1. This diffusion
is known as the predeposition or "predep" diffusion (see OP-D
and OP-E). The rear surface of the wafer will be protected with oxide in
this diffusion. We will use both n-type and p-type substrates to facilitate
comparisons of device characteristics during the testing phase of the experiment.
After the wafer has been suitably cleaned, it will then be subjected to
another diffusion, called the redistribution or "drive" diffusion,
this time without the dopant source. The idea here is to redistribute the
dopant such that its concentration is more uniform. This diffusion will
be initiated in an oxygen atmosphere so that another layer of oxide is grown
simultaneously on the wafer to protect the doped regions. See OP-F.
The next step in our wafer fabrication will use a second photoresist (PR)
process using Mask Level 2 (labeled G for "gate" in the
upper right corner of the mask), p. 40, to delineate areas for growth of
a high quality gate oxide. After resist processing, a buffered HF (BHF)
etch will completely remove previously grown oxides, leaving a clean silicon
surface over the gate region of our MOSFET and over our MOS capacitors.
The resist will then be cleaned off, and the Dry Oxide Furnace used to grow
a thin, high quality oxide. We will perform these gate oxide growths with
chlorine injection to improve the quality of the gate oxide.
After gate oxide growth, a third PR process using Mask Level 3 (labeled
C for "contact" in the upper right corner of the mask),
p. 41, will be used to cut holes down to the doped regions in the silicon,
through which contacts can be made. Aluminum will then be vacuum evaporated
over the entire wafer, and a 4th PR process utilized to etch the contact
pattern using Mask 4 (labeled M for "metal" in the upper
right corner of the mask), p. 42.
Once the front metalization pattern is etched, aluminum will be evaporated
onto the backside of the chip to help form the substrate contact. Before
metalization we damage the back with sandpaper to help insure an ohmic contact
will be formed (strictly speaking, the damage will insure that any Schottky
diode formed between the aluminum and the silicon will be very leaky).]
Finally, you will form the ohmic Al-Si contacts by annealing. This is a
process in which the components of a system are heated to a temperature
below the system's eutectic point. (The melting point of a given alloy of
one substance in another depends upon the percentages of the materials present.
That point on a phase diagram of temperature vs. percent of each parent
material present where a temperature minimum occurs in the liquidus line
is known as the eutectic point.) The eutectic point for the Al-Si system
is 576C. You will use a temperature of 450C which permits the aluminum
atoms to move around and spread more uniformly over the silicon surface.
In addition, during annealing, the aluminum can diffuse into the silicon
itself. This will ensure low resistance contacts to the silicon devices.
This concludes the device processing.
Processing Description: Materials Properties Test Chips
Starting with the oxidized wafers, the ellipsometer is used (see OP-R) to
measure the initial field oxide thickness. After measurement, a simple pattern
is etched through the oxide. This pattern will simply uncover one-half of
the MPT samples. A predep (at the same time as your device chips) is then
performed. We can now measure the sheet resistance of the predep layer using
the four-point probe (see OP-H). Note this allows you to infer the sheet
resistance of the doped regions on your device chips.
After cleaning, we will subject the MPT samples to a drive-in diffusion
(again, at the same time as the device samples). After the drive, the oxide
thickness grown during the drive is measured, then completely etched away
in buffered HF. You will now be able to measure the sheet resistance of
the doped layer (note it will not be the same as it was after the predep),
as well as the resistivity of the wafer substrate (by measuring on the half
of the substrate that was covered with oxide during the predep). Again,
this will give you information about certain areas on your device chips
at this point in the process.
The last high temperature process step performed on your samples is the
gate oxide growth step. The oxide-free MPT samples will be included with
your device chips during the TCE dry oxidation (see OP-C). After completion,
you will measure the oxide thickness grown on the MPT chips; this will give
you the gate oxide thickness on your device samples. We will also use a
technique called junction grooving (see OP-N and Ghandhi, pp 196-197) to
find the depth of the p-n junctions below the wafer surface. Note this step
is destructive, requiring the grinding of a groove in the surface of your
MPT samples. If possible, after determining the junction depth, you will
etch all oxide off the MPT chips so that the sheet resistance of the doped
layers can be measured again. This is necessary since the dopants will have
diffused during the high temperature gate oxidation. Note that based on
the measurements made on your MPT samples, you will now have all the materials
properties necessary to analyze the devices on your patterned device chips.
General Comments
In order to complete all the processing required, you must keep up with
the schedule on pp. 5-7. In particular, there are three steps that will
be batch processed, with everyone's chips together: process step 5, lab
4, the predep process; process step 7, lab 5, the drive-in process; and
process step 11, lab 7, the gate oxidation process.You MUST have all
necessary processing and measurements done before each of these steps so
that you samples are ready for the batch process. Catch-up lab periods
(outside of normal lab times) will be held before each of these critical
steps to allow you extra processing time, if necessary.
Before coming to each lab read the appropriate Processing Description,
and any operating procedures used in that section. Answer any pre-lab
questions assigned. Use the checklist in the Processing Description at all
times to ensure that each step is completed. Do not use the checklist as
a substitute for reading and understanding all procedures and instructions
BEFORE lab begins.
Because of limited equipment and space, different groups will do different
portions of a process at different times. In particular, some groups will
be making measurements on the MPT samples while others are processing their
device chips. For example, during lab period 5 two groups will be using
the ellipsometer and 4-point probes on their MPT samples, while the other
two groups will be performing the 2nd photoresist process (process step
8) on their device chips. In lab 6 these groups will reverse roles.
Always consult your lab TA at the beginning of the lab period for updated
processing instructions. Check with the TA if any mistakes are made
in processing or if you do not complete the procedure outlined for that
period. Please be considerate of the other groups in the lab, and do not
monopolize the processing equipment.
Lab Schedule: see course syllabus for due
dates for asignments
Process Device Chip Materials Properties Test Chip
Step
on one p-type, one n-type on one p-type, one n-type
pre-oxidized chip pre-oxidized chip
Lab 2 & 3
1 ellipsometric oxide thickness
measurement
2 Photoresist 1: diffusion, Photoresist 1: half mask
Holberg Mask Level 1
3 Etch 1st diffusion windows Etch oxide from half of chip
4 Strip all resist Strip all resist
Lab 4
5 p-type sample: phosphorus p-type sample: phosphorus
predep, 20 min n-type sample: predep, 20 min n-type sample:
boron predep, 30 min boron predep, 30 min
6 Strip boro/phospho-silicate Same as device chips; 4-point
glass in BHF probe for sheet R
Lab 5 & 6
7 Both p- & n-type: drive-in, Same as device chips; after
1100deg.C, 30 min. drive: oxide thickness
8 PR 2: gate ox pattern, Holberg NA
Mask Level 2
9 BHF oxide etch Same as device chips; 4-point
probe for sheet R
10 Strip PR NA
(Process Flow Summary cont.)
Process Device Chip Materials Properties Test Chip
Step
Lab 7 & 8
11 Gate oxidation: 1100deg.C, Same as device chip; after ox:
with TCE oxide thickness
12 PR 3: contact windows, Holberg NA
Mask Level 3
13 BHF oxide etch same as device chip; 4-pt probe
for final Rs; junction groove
for xj
Lab 9-11
14 Backside damage
15 Strip PR
16 Front side Al evaporation
17 PR 4: Metal contacts, Holberg
Mask Level 4
18 Aluminum contact etch
19 Strip PR
20 Backside metallization
21 Form contacts