Course Syllabus: EE 440/396K Fall 2001 UNDER CONSTRUCTION

Microelectronics/VLSI Fabrication Techniques

 

EE 440 Unique Number 15230; EE 396K Unique Numbers 15725, Fall 2001, M-W-F 8:00-9:00, ENS 302

Instructor: Dean Neikirk, ENS 634, phone 471-4669; MERB 1.606F, 471-8549; e-mail: neikirk@mail.utexas.edu

TA's:, not yet determined

UT Blackboard site:  http://courses.utexas.edu/  ; THIS SITE REQUIRES A UT-EID TO ACCESS

Web site:  http://weewave.mer.utexas.edu/DPN_files/courses/FabLab/IC_Fab_class.html

Office Hours: M-F, 9:00-10:00, W: probably 1-2, I’ll confirm this after classes start; or by arrangement

Prerequisites:  EE 339 Introduction to Electron Devices or equivalent

 

Objectives:   The purpose of this course is to provide students with technical background and hands-on laboratory experience in silicon device fabrication.  The course involves approximately three hours of lecture and three hours of laboratory per week for one semester.  The following is an outline of subjects to be presented in the lecture portion of the course and experiments to be performed in the laboratory.


Lecture:

1. Semiconductor review and survey of IC processing.

2. Silicon crystal growth and wafer preparation.

3. Oxidation.

4. Doping techniques: diffusion, ion implantation.

5. Deposited thin films: polysilicon, silicon dioxide, silicon nitride, metals, silicides.

6. Metallization and contacts.

7. Epitaxial growth.

8. Lithography: optical, electron beam, X-ray.

9. Etching techniques: wet chemical, dry plasma.

10. Yield considerations and contamination.

 


Laboratory:

Fabrication and testing of diffused resistors and MOS devices. In these experiments masks will be used containing arrays of the various discrete devices.

A. Photolithography.

B. Predep and drive.

C. Gate Oxide Growth.

D. Contact deposition and annealing.

E. Junction depth and sheet resistance measurements.

F. I-V and breakdown measurements.

G. MOS capacitor testing.

H. MOSFET testing.

I. Resistor testing.

 


Text Book:  J. Plummer, M. Deal, and P. Griffin, Silicon VLSI Technology. Upper Saddle River, New Jersey: Prentice Hall, Inc., 2000.

Useful references:

S. A. Campbell, The Science and Engineering of Microelectronic Fabrication: Oxford University Press, 1996.

VLSI Fabrication Principles by S.K. Ghandhi; VLSI Technology editor S.M. Sze

Device Electronics for Integrated Circuits by R.S. Muller and T.I. Kamins

MOS Physics and Technology by E.H. Nicollian and J.R. Brews

Physics of Semiconductor Devices ed. S. Sze, Solid State Electronic Devices, Streetman

 

Grades

Your grades will be based upon performance in lab, lab reports, homework, and exams. Details of work expected in conjunction with lab are given in the lab manual (see next page).


 

The weighting for different areas is :

Homework                  15%

Exam I                       20%

Exam II                      20%

Lab grade                    20%

Final                          25%

              100%

 


 

The worst-case grades will be based on:

A                    100-90% of

    total points available

B                    80-89%

C                   70-79%

D                    55-70%

F                   0-55%


The University of Texas at Austin provides upon request appropriate academic adjustments for qualified students with disabilities.  For more information, contact the Office of the Dean of Students at 471-6259, 471-4641 TDD or the college of engineering director of students with disabilities at 471-4382. Please see http://www.utexas.edu/depts/dos/ssd/

OFFICIAL UNIVERSITY CALENDAR AVAILABLE AT: http://www.utexas.edu/student/registrar/00-01long.html

LAST DAY TO DROP:  4TH DAY OF CLASSES (Sept. 5); BETWEEN THEN AND SEPT. 27 MUST GO TO DEAN'S OFFICE; AFTER Sept. 27 THERE MAY BE AN ACADEMIC PENALTY; after Oct. 25 drops allowed by UT only for extreme non-academic reasons.  Notice of planned absences for the observance of religious holy days must be submitted two weeks in advance of the date of the absences. (See General Information, chapter 4, for requirements.)


Course Evaluation:  University and optional in-house survey during last week of class.

 

Policy on CHEATING:

You are expected to do your own work at ALL times.  I expect you will often discuss assignments, but you MUST do your own ORIGINAL written work.  Any evidence of cheating or plagiarism* will be treated as grounds for FAILURE in the class. 

 

The following is extracted from the document "On Being A Scientist: Responsible Conduct In Research" by the COMMITTEE ON SCIENCE, ENG, NATIONAL ACADEMY OF ENGINEERING, INSTITUTE OF MEDICINE, NATIONAL ACADEMY PRESS, Washington, D.C. 1995. 

 

Copyright © 1994 by the National Academy of Sciences. All rights reserved. This document may be reproduced solely for educational purposes without the written permission of the National Academy of Sciences.  Internet Access: This report is available on the National Academy of Sciences' Internet host. It may be accessed via World Wide Web at http://www.nas.edu, via Gopher at gopher.nas.edu, or via FTP at ftp.nas.edu.

 

*"A CASE OF PLAGIARISM

                "May is a second-year graduate student preparing the written portion of her qualifying exam.  She incorporates whole sentences and paragraphs verbatim from several published papers.  She does not use quotation marks, but the sources are suggested by statements like '(see . . . for more details).'  The faculty on the qualifying exam committee note inconsistencies in the writing styles of different paragraphs of the text and check the sources, uncovering May's plagiarism.

                "After discussion with the faculty, May's plagiarism is brought to the attention of the dean of the graduate school, whose responsibility it is to review such incidents.  The graduate school regulations state that 'plagiarism, that is, the failure in a dissertation, essay, or other written exercise to acknowledge ideas, research or language taken from others' is specifically prohibited.  The dean expels May from the program with the stipulation that she can reapply for the next academic year." [ URL: http://www.nap.edu/readingroom/books/obas/contents/misconduct.html#Plagiarism ]

 

                "A broad spectrum of misconduct falls into the category of plagiarism, ranging from obvious theft to uncredited paraphrasing that some might not consider dishonest at all.  In a lifetime of reading, theorizing, and experimenting, a person's work will inevitably incorporate and overlap with that of others.  However, occasional overlap is one thing; systematic use of the techniques, data, words, or ideas of others without appropriate acknowledgment is another."  [ URL: http://www.nap.edu/readingroom/books/obas/contents/appendix.html#Plagiarism ]

 

 

Special Note to EE396K students:

Since you are enrolled for graduate credit, I will expect you to do more than the undergraduates.  This will take the form of a term lab project or a term review paper (approximately 5-10 type-written pages long) on a topic related to device fabrication or processing.  You must pick a topic and clear it with me by Weds., Oct. 4. The paper should review current work in the literature related to your topic. It is due on Fri., Dec. 8.  More details to follow.  The project/paper grade will be factored into your lab grade.

 

Laboratory Manual

You must purchase a laboratory manual.  It will be available from HKN here in ENS. The manual contains essential information on the laboratory, lab procedures, and work required for your lab grade.  YOU MUST GET A COPY AS SOON AS POSSIBLE.  As new materials become available I will notify you.

 

Copies of the viewgraphs I use in class will be available via our class home page.


Readings should be completed BEFORE class (subject to revision as I get behind).  Readings from Sze or Ghandhi are optional.

 

Lecture

Date

Topic

Sze 1st ed

Ghandhi

2nd ed

Campbell

 

1

8/30

Introduction, Lab assignments

 

 

 

 

2

9/1

CMOS Process Overview

 

 

3-9

 

3

9/6

Review of semiconductors

1-8

1-23

10-20

 

4

9/8

Orientation effects, impurities

 

23-45

 

 

5

9/11

Defects; Lab Report 0 due in lecture!!

14-17

45-63

 

 

6

9/13

Crystal Growth

17-23

102-113

21-35

 

7

9/15

Crystal growth cont

23-31

113-134

 

 

8

9/18

Impurities in CZ, Gettering, Oxygen in Si

31-51

134-144

 

 

9

9/20

Basic oxidation processes

98-106

451-457

68-77

 

10

9/22

Oxidation kinetics, Halogenic oxidation

106-110

458-463

 

 

11

9/25

Doping effects; Critique of Lab Report 0 due

111-115

463-470

84-94

 

12

9/27

Thin oxides, OSF's, mobile charge

115-125

470-485

77-83

 

13

9/29

Diffusion, Fick's laws, Diffusion profiles, Fick's 2nd law

272-279

150-159

39-47

 

14

10/2

Vacancy-Impurity interactions

279-286

159-171

47-52

 

15

10/4

diffusion continued, Graduate Student paper topics due

 

171-197

52-65

 

16

10/6

Boron & phosphorus diffusion; review

286-297

210-224

 

 

17

10/9

EXAM I

 

 

 

 

18

10/11

Ion implantation

327-340

368-389

98-112

 

19

10/13

Implantation: channeling, damage

340-348

389-407

112-123

 

20

10/16

Annealing of implants; applications

348-362

407-443

 

 

21

10/18

Irvin Curves, evaluation of doped layers

299-307

235-250

 

 

22

10/20

Evaluation techniques cont

 

 

 

 

23

10/23

Hall effect, Lab Report I due

 

 

 

 

24

10/25

kinetic gas theory, step coverage, physical vapor deposition

 

 

 

 

25

10/27

thermal evaporation, sputtering

 

 

 

 

26

10/30

Chemical Vapor Deposition, kinetic gas theory, poly Si

233-248

510-527

 

 

27

11/1

poly, oxide, nitride

248-269

527-546

 

 

28

11/3

Epitaxy

55-63

258-272

 

 

29 

11/6

Autodoping, pattern shift; Critique of Report I due

63-79

284-312

 

 

30

11/8

Metallization

375-396

548-570

 

 

31

11/10

Contacts

396-409

 

 

 

32

11/13

Electromigration

409-418

 

 

 

33

11/15

EXAM II

 

 

 

 

34

11/17

Lithography

141-155

662-674

 

 

35

11/20

Mask aligners, Lab Report II due

 

674-685

 

 

36

11/22

Resists

 

 

 

 

37

11/27

Advanced Lithography

155-180

685-700

 

 

38

11/29

Etching: bias & selectivity

196-199

613-620

 

 

39

12/1

Selectivity cont

206-210

 

 

 

40

12/4

Plasma etching

184-196

620-645

 

 

41

12/6

Plasma processing;

212-228

 

 

 

42

12/8

Review; Graduate Projects/Papers Due; Critique of Report II due; Lab Report III due

 

                               FINAL: Friday, Dec. 15, 9:00 am - 12:00 noon


 

WWW resources for IC Fab:

 

Our 440/396K class:

http://weewave.mer.utexas.edu/DPN_files/courses/FabLab/IC_Fab_class.html .

 

The semiconductor subway:

http://www-mtl.mit.edu/semisubway.html .

 

University  of Illinios IC Fab Class:

http://www.ece.uiuc.edu/ece344/ .

 

All these applets are accessible from the main page at Buffalo: http://jas2.eng.buffalo.edu/applets/education/index.html

 

 

Newsgroups:

 

sci.electronics.cad

sci.engr.semiconductors

sci.materials

sci.optics

sci.physics

sci.physics.research

sci.techniques.microscopy

comp.lsi